1. Field
One embodiment of the invention relates to a decoding device for decoding a codeword, which includes information symbols and a parity check code, in accordance with a check matrix, and to a storage device and a decoding method.
2. Description of the Related Art
In general, a storage device or a communication device makes use of an error correction function for correcting an error in information symbols. In most of error correction functions, a parity check code is used.
Japanese Patent No. 2539343 discloses an error correction circuit which corrects an error in a data field including parity bits.
In usual cases, a parity check code (also referred to as “parity bits”) corresponding to information symbols is generated in accordance with a generator matrix. In addition, a codeword, which includes the information symbols and the generated parity check code, is decoded in accordance with a check matrix corresponding to the generator matrix. In a decoding process for decoding the codeword, a syndrome of the codeword is calculated in accordance with the check matrix. The calculated syndrome is converted to an error address which is indicative of an error position in the information symbols.
The process for converting the calculated syndrome to an error address can be executed by using a combinational circuit. However, if the data length (the number of bits) of the information symbols is large, the circuit scale of the combinational circuit that is necessary for the converting process becomes very large.
Thus, in a decoding device that handles information symbols of great data length, it is not realistic to execute the conversion process by the combinational circuit. Hence, in order to reduce the circuit scale of the decoding device, a novel function is needed for easily determining the error address from the syndrome.